Configuration information of a circuit may be written into a semiconductor integrated circuit to implement functionality in a reconfigurable semiconductor integrated circuit such as FPGA (Field-Programmable Gate Array).
The reconfigurable semiconductor integrated circuit includes a CLB (Configurable Logic Block) provided with a plurality of basic logic elements, a SB (Switch Block), a CB (Connection Block) and a wiring portion connecting these components with each other. The semiconductor integrated circuit equipped with these components is adapted to programmably connect the CLB such that a wiring length is relatively longer and a wiring capacitance is relatively larger compared to the ASIC (Application Specific Integrated Circuit). Therefore, power consumption of the wiring portion tends to be large.
There is an electrical charge recycling technique as a power saving technique applied to the field of the ASIC. In a logical circuit, when a signal value is changed from “1” to “0”, all the electrical charge charged in the wiring capacitor is discharged, and power of CVDD2/2 is consumed where the value of the wiring capacitance is C and the power supply voltage is VDD. In contrast, in the electrical charge recycling technique, when the charged electrical charge is discharged, some of the electrical charge is stored in a separate capacitor and then, the electrical charge is reused later when the signal value is changed from “0” to “1” so as to reduce the power consumption.
Further, there is a clock resonance scheme as a type of the electrical charge recycling technique. In the clock resonance scheme, an inductor is added to a clock wiring network and an LC resonance circuit is implemented to be resonated by the inductance of the inductor and the capacitance of the clock wiring. Accordingly, electrical charge is reused between the inductor and the capacitor of the clock wiring to reduce the power of the clock wiring network.
See, for example, Japanese Patent Laid-Open Publication No. 2001-195163 and Japanese Patent Laid-Open Publication No. 2011-250107.
See, for example, non-patent literature 1: S. Chan, K. Shepard, and P. Restle, “Uniform-phase uniform-amplitude resonant-load global clock distributions”, Solid-State Circuits, IEEE Journal of, vol. 40, no. 1, pp. 102-109, January 2005; and non-patent literature 2: L. McMurchie and C. Ebeling, “Pathfinder: A negotiation-based performance-driven router for fpgas”, in ACM/SIGDA International Symposium on Field Programmable Gate Arrays, Monterey, Calif., USA, 1995, pp. 111-117.
However, when the conventional electrical charge recycling technique as described above is intended to be applied to the semiconductor integrated circuit to reduce the power consumption, the timing constraints may not be satisfied due to the increase of the delay time caused by the transfer of the electrical charge.